The present application claims priority to Japanese Application(s) No(s). P2000-325173 filed Oct. 25, 2000, which application(s) is/are incorporated herein by reference to the extent permitted by law.
1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device including a step of exposing a fine pattern with precise alignment, and an apparatus of automatically adjusting a semiconductor exposure pattern for use in the method.
2. Description of Related Art
In semiconductor devices such as so-called integrated circuits, a finer pattern and a higher integration degree are recently required in association with a larger capacity of memory or a larger number of functions of logics in a CPU (Central Processing Unit). In addition to the integrated circuits, a finer pattern and a higher integration degree are similarly required, for example in imaging devices such as CCDs (Charge Coupled Device), as a type of the semiconductor devices by making good use of a fine pattern forming technique which has been developed in the integrated circuits.
In the semiconductor devices such as the integrated circuits, an exposure step was typically performed with a step and repeat method using a so-called stepper exposure unit before a generation in which a 0.25 xcexcm design rule is applied. In a generation in which a 0.25 to 0.18 xcexcm design rule is applied or in a later generation, however, a single manufacturing process for a semiconductor device has employed both an exposure step with the step and repeat method and an exposure step with a scan method using a so-called scanner exposure unit (also referred to as xe2x80x9ca scan exposure unitxe2x80x9d).
The exposure step in the step and repeat method involves the use of a reticle having a mask pattern formed thereon at a predetermined scaling factor such as 5 times or 10 times in some cases for performing an exposure step to scale down the pattern onto a semiconductor wafer at a predetermined scaling factor. While this exposure step has an advantage of high throughput, it does not necessarily function well for the exposure process of a pattern with a line width design rule of less than 0.25 xcexcm because of limits of resolution or difficulty in making fine adjustments of the pattern during the exposure process.
On the other hand, in the exposure step in the scan method, an exposure step of one mask pattern for one chip involves irradiating an elongated slit area with light and scanning the entire mask pattern through the slit area to perform an exposure step of the entire shot. Since this exposure step allows precise exposure of a very fine pattern with high resolution and permits many parameters for shape correction with a higher degree of freedom, fine adjustments of patterns can be made during the exposure step. In this exposure step, however, both stages of a reticle and a wafer must be controlled simultaneously and thus equipment therefore becomes complicated to cause a higher process cost than the step and repeat method.
To address this, it is becoming popular practice to employ such scan method to perform the exposure in a device pattern forming step which strongly requires precise formation of a fine pattern of less than 0.25 xcexcm such as each structural part of a device or a wiring pattern on the one hand, and on the other hand, to employ the step and repeat method to perform an exposure step in a step of forming a so-called rough-layer pattern with a relatively low fineness of 0.25 xcexcm or more, for example a resist pattern for use in an ion implantation step.
Typically, since the step of forming a pattern of a rough-layer or the like is performed after the device pattern forming step, the exposure step in the step and repeat method is performed after the exposure step by the scan method.
The exposure step in the step and repeat method, however, allows only scale-up/scale-down and parallel shifts over the entire exposure area with regard to adjustments of the shape or a position of a pattern, so that it has a lower degree of freedom than the exposure step in the scan method. Thus, if an offset occurs in the shape or the position of the pattern in the exposure step of the scan method performed earlier, a problem arises in that the existing offset cannot be corrected precisely in some cases in the exposure step of the step and repeat method performed later.
For example, if the exposure step in the scan method results in distortion in an aspect ratio over the entire exposure area, the exposure step with the step and repeat method performed thereafter cannot adjust the dimensions independently in the vertical and horizontal directions over the entire exposure area. For this reason, if adjustments are made to correct the offset only in one of the directions, the offset in the other direction may remain uncorrected or the amount of the offset may increase.
Alternatively, it is contemplated that an effective approach is to prevent occurrence of an offset in the shape or a position in a pattern in the exposure step in the scan method. To realize the approach, however, it is necessary to add a step of forming a marking for indicating a reference point of alignment in the exposure step by the scan method on a wafer to be patterned prior to the exposure step in the scan method since the exposure step in the scan method is typically performed earlier. The necessity causes an additional disadvantage of more complicated manufacturing steps or a lower throughput.
The present invention has been made in view of such problems, and it is an aspect of the present invention to provide a method of manufacturing a semiconductor device and an apparatus of automatically adjusting a semiconductor pattern which can precisely correct a difference in the shape or position of a pattern between an exposure step as a first patterning step and an exposure step performed after the above exposure step as a second patterning step, wherein the first patterning step has a predetermined degree of freedom for allowing exposure of a high-fineness pattern, for example with the scan method, and the second patterning step has a lower degree of freedom than the first patterning step, for example with the step and repeat method.
A method of manufacturing a semiconductor device according to the present invention comprises the steps of: a first patterning step including a step of exposing a first pattern on a semiconductor substrate in a shape adjusted with a predetermined degree of freedom; and a second patterning step including a step of exposing a second pattern, while the second pattern is aligned with the first pattern, in a shape adjusted with a degree of freedom equal to or lower than the degree of freedom in the first patterning step with an exposure method or an exposure unit different from that in the first exposure step, wherein a difference in the shape and/or position between the first pattern and the second pattern is measured, and information on the difference is relied on to adjust the shape of a first pattern in a first patterning step performed next the first patterning step in which the difference is measured or later.
An apparatus of automatically adjusting a semiconductor exposure pattern according to the present invention is used in a process of manufacturing a semiconductor device comprising the steps of: a first patterning step including a step of exposing a first pattern on a semiconductor substrate in a shape adjusted with a predetermined degree of freedom; and a second patterning step including a step of exposing a second pattern, while the second pattern is aligned with the first pattern, in a shape adjusted with a degree of freedom equal to or lower than the degree of freedom in the first patterning step with an exposure method or an exposure unit different from that in the first exposure step, the apparatus comprising: pattern measuring means for measuring a difference in the shape and/or position between the first pattern and the second pattern; and pattern adjusting means for relying on information on the difference to adjust the shape of a first pattern in a first patterning step performed next the first patterning step in which the difference is measured or later.
In the method of manufacturing a semiconductor device according to the present invention, a difference in the shape or position is measured between the first pattern obtained with the exposure method in the first patterning step having a high degree of freedom for the shape or position of an exposure pattern and the second pattern obtained with the exposure method in the subsequent second patterning step having a lower degree of freedom in a manufacturing process of a semiconductor device, and the information on the difference is relied on to adjust a first pattern in a first patterning step with a high degree of freedom in the next manufacturing step cycle of the semiconductor device, thereby precisely align the shape or position of the first pattern with the second pattern in the second patterning step with a lower degree of freedom.
In the apparatus of automatically adjusting a semiconductor exposure pattern according to the present invention, the pattern measuring means measures a difference in the shape or position between the first pattern and the second pattern in the aforementioned manufacturing method, and the pattern adjusting means adjusts the first pattern in the first patterning step. Thus, the method of manufacturing a semiconductor device as described above is embodied.
As described above, according to the method of manufacturing a semiconductor device in an embodiment of the present invention or the apparatus of automatically adjusting the semiconductor exposure pattern in an embodiment of the present invention, a difference in the shape or position is measured between the first pattern obtained with the exposure method in the first patterning step and the second pattern obtained with the exposure method in the second patterning step having a lower degree of freedom in a manufacturing step cycle of a semiconductor device, and the information on the difference is relied on to adjust the first pattern in a first patterning step with a high degree of freedom such that the shape or position of the first pattern matches the second pattern in a second patterning step with a lower degree of freedom in the next manufacturing step cycle or later of the semiconductor device. Thus, the shape or position of the first pattern in the first patterning step with a high degree of freedom can advantageously match (be aligned with) the second pattern precisely in the second patterning step with a low degree of freedom in the next manufacturing step cycle or later.
In addition, according to the method of manufacturing a semiconductor device in an embodiment of the present invention, a difference in the shape or position is measured between the first pattern and the second pattern in a lot in the prototyping stage and the measurement results are relied on to adjust the shape of the first pattern in the first patterning step for a production lot. Thus, even if an offset in the shape or position enough to be recognized as a defective item occurs in a lot at the prototyping stage, the first pattern can be precisely aligned with the second pattern in a production lot based on the information on the difference, thereby making it possible to advantageously prevent the occurrence of a defective item to improve manufacturing yields. Furthermore, since the first pattern can be aligned with the second pattern without forming a reference pattern for alignment or the like prior to the first patterning step in a manufacturing process of each wafer or semiconductor device in a production lot, it is possible to avoid a complicated manufacturing method due to an additional step of forming such a reference pattern.